There's Plenty of Room at the Bottom - and at the Top
Tsu-Jae King Liu
UC Berkeley
Abstract:
The
virtuous cycle of integrated-circuit (IC) technology advancement has
been sustained for over 50 years, resulting in the proliferation of
information and communication technology with dramatic economic and
social impact. Industry experts predict that the pace of increasing
transistor density will slow down dramatically within the next 5 years,
however, due to fundamental limits of the conventional photolithographic
patterning process. Scaling of IC feature sizes beyond the resolution
limit of lithography has been enabled by multiple-patterning techniques,
but at significant incremental cost. In the first part of this seminar,
I will describe a more cost-efficient approach for defining
sub-lithographic features, to help extend the era of Moore’s Law.
Beyond
Moore’s Law, the proliferation of mobile electronic devices and the
emergence of applications such as wireless sensor networks and the
Internet of Things have brought energy consumption to the fore of
challenges for future information-processing devices. In the second part
of this seminar, I will discuss how the computational functionality and
energy efficiency of ICs can be enhanced by reconfigurable interconnect
technology, to sustain the information technology revolution.
Bio:
Tsu-Jae
King Liu received the B.S., M.S., and Ph.D. degrees in Electrical
Engineering from Stanford University. From 1992 to 1996 she was a Member
of Research Staff at the Xerox Palo Alto Research Center (Palo Alto,
CA). In August 1996 she joined the faculty of the University of
California, Berkeley, where she currently holds the TSMC Distinguished
Professorship in Microelectronics in the Department of Electrical
Engineering and Computer Sciences, and also serves at the campus level
as Vice Provost for Academic and Space Planning.
Dr.
Liu’s research contributions in the area of semiconductor devices and
technology include the DARPA Significant Technical Achievement Award
(2000) for development of the FinFET, the IEEE Kiyo Tomiyasu Award
(2010) for contributions to nanoscale MOS transistors, memory devices,
and MEMs devices, the Semiconductor Industry Association Outstanding
Research Award (2014), and the Semiconductor Research Corporation
Aristotle Award (2016). She has authored or co-authored over 500
publications and holds over 90 U.S. patents, is a Fellow of the IEEE and
an elected member of the U.S National Academy of Engineering. She
presently serves as Editor-in-Chief for IEEE Electron Device Letters (the flagship journal of the IEEE Electron Devices Society), and on the Board of Directors for Intel Corporation.
Hosted by Professor Miryung Kim
REFRESHMENTS at 3:45 pm, SPEAKER at 4:15 pm
THURSDAY, MAY 18, 2017
PLACE: 3400 BOELTER HALL
TIME: 4:15 – 5:45 PM